Hardware emulators are programmable devices used in the verification of logic designs. A common method of logic design verification is to use processors to emulate the design. These processor-based emulators sequentially evaluate combinatorial logic levels, starting at the inputs and proceeding to the outputs. Each pass through the entire set of logic levels is called a Target Cycle; the evaluation of each individual logic level is called an Emulation Step.
Speed is a major selling factor in the emulator market, and is a well known problem. The purpose of this invention is to significantly improve our emulator's speed.
Our invention is an improvement over that disclosed in U.S. Pat. No. 5,551,013, “Multiprocessor for Hardware Emulation,” issued to Beausoleil, et al., where a software-driven multiprocessor emulation system with a plurality of emulation processors connected in parallel in a module has one or more modules of processors to make up an emulation system. Our current processor-based emulator consists of a large number of interconnected processors, each with an individual control store, as described in detail in the U.S. Pat. No. 5,551,013. It would be desirable to improve the speed of this emulator.
While not suitable for our purposes, but for completeness, we note that FPGA-based emulation systems exist that achieve high speeds for small models. However, FPGA-based emulators are inherently I/O bound, and therefore perform poorly with large models. In general, the problem of high-speed emulation of large models had not been solved.